1. Field of the Invention
This application is based upon and claims the benefit of the priority of Japanese patent application No. 2012-039581, filed on Feb. 27, 2012, the disclosure of which is incorporated herein in its entirety by reference thereto.
The present invention relates to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory device including a function of relieving a defect in a bit line.
2. Description of Related Art
Semiconductor memory devices include a memory cell array in which memory cells are arranged in a two-dimensional matrix form. An address multiplexing scheme is widely employed in the semiconductor memory devices. In this scheme, when accessing one of the memory cells arranged in the memory cell array, a row address for selecting a word line and a column address for selecting a bit line are input in this stated order.
Among the semiconductor memory devices that have employed the address multiplexing scheme, there are some semiconductor memory devices based on a hierarchical bit line scheme. The hierarchical bit line scheme is the one in which bit lines are hierarchized into global bit lines and local bit lines, one sense amplifier circuit is connected to each global bit line, a plurality of segmented local bit lines are arranged along the global bit line, and one of the local bit lines is selectively connected to the global bit line.
JP Patent No. 4802515, which corresponds to US7574648B2 describes a semiconductor memory device in which a circuit for correcting erroneous read data (i.e. data that have been read erroneously) by using an error correction code (ECC) is disposed adjacent to sense amplifier circuits.